When new integrated circuit chips are being developed and tested, it is desirable to access internal nodes within the chip for measuring voltages, observing waveforms, or observing delays at the nodes. In the past, when internal features were larger, it was possible to place a probe on any internal node and measure the voltage or waveform. But with significant shrinkage, internal probing of a line within the integrated circuit is no longer possible, so probe pads are needed. And with the increase of complexity, there are many places to probe and it is not practical to place probe pads everywhere you want to observe a signal. E-beam probing of internal nodes is also possible, but expensive and time-consuming, so most circuits, at least in test chips, are designed to include circuits to bring one of several signals to a probe pad for observation.
Sample and Hold
For testing periodic signals, sampling oscilloscopes can illustrate the waveform of a periodic signal by taking successive samples from different parts of successive cycles of the periodic signal to generate and display a composite graph to illustrate the waveform. The paper “Applications of On-Chip Samplers for Test and Measurement of Integrated Circuits” by Ron Ho, Bharadwaj Amrutur, Ken Mai, Bennett Wilburn, Toshihiko Mori, and Mark Horowitz, Stanford University, ©1998 IEEE, describes a system that includes a circuit inside the chip to iteratively look at a selected point in the chip over successive cycles, sampling later and later points of the cycle in successive cycles, and putting that sampled signal on an oscilloscope to see the waveform. This method shows noise coupling or other glitches, and is thus ideal for looking at the particular internal point in the chip. But it requires taking many sample points, and manually observing an oscilloscope, and thus it is a time consuming method. Also, as signals and clocks get faster and faster, the difference between the signal clock and sample clock must get smaller and smaller. To accurately represent the rise time of, say, 10 picoseconds in a 1 nanosecond signal cycle will require on the order of 1000 samples to give 1 picosecond resolution. So if the signal clock is 1 gigahertz, the sample clock may need to be 1.001 gigahertz to give the 1000 samples. And this is difficult to achieve, requiring expensive frequency control. Also, it requires human manipulation. This method can not be implemented automatically by a tester computer. It would be desirable to use a testing method that could be implemented automatically by a tester computer, and would not require elaborate circuitry within the chip to produce accurate results.